1. Field of the Invention
The present invention relates generally to solid state memory controllers, and more particularly to a sequencer for solid state memory controllers.
2. Description of Related Art
The performance and capacity of a solid state drive depend on parallelism on accessing solid state memory devices, e.g., flash memory devices. FIG. 1A illustrates a currently available system for controlling access to solid state memory devices. As shown, a flash controller 101 may communicate with a host 102 through a buffer 103 on one side, and communicate with flash memory devices D0-D7 through channels CH0-CH7 on another side, with each channel dedicated to one memory device. The flash memory devices D0-D7 may be NAND or NOR flash memory devices. The flash controller 101 may have an ECC (Error Correcting Code) section 1011, a formatter 1012, a flash I/F controller 1013, and a sequencer 1014. The ECC section 1011 may correct errors in a data flow passing through it, the formatter 1012 may convert the format of a data flow from the host 102 to conform with requirements of the flash I/F controller 1013 and convert the format of a data flow from a flash memory device to conform with requirements of the host 102, and the flash I/F controller 1013 may be an interface between the flash controller 101 and the flash memory devices D0-D7. Firmware 104 may generate control signals to the flash controller 101. A sequencer 1014 may receive the control signals from the firmware 104 and control the ECC section 1011, the formatter 1012 and the flash I/F controller 1013 accordingly.
During a write operation to the flash memory device D0, the flash controller 101 may receive data from the host 102 via the buffer 103. In the flash controller 101, the data from the host 102 may pass through the ECC section 1011, the formatter 1012 and the flash I/F controller 1013, and finally be sent to an internal buffer in a flash memory device. The data may then be moved from the internal buffer to the flash memory device.
FIG. 1B illustrates the waveform of a write operation in the system shown in FIG. 1A. As shown, for the flash memory device D0, data may be transferred from the flash controller 101 to an internal buffer in the device D0 from time t0 to t1, and may be moved from the internal buffer to the device D0 from t1 to t4. Then the device D0 may send out a confirmation indicating that the write operation is finished, so that the next operation request may start to be processed. Although the host 102 is not involved in the transaction between the internal buffer and the device D0, t1 to t4, the host 102 cannot process the next operation request until t4. Since the time period for t1 to t4 is much longer than the time period from t0 to t1, a lot of host time is wasted. In one example, the ratio between the time period from t0 to t1 and the time period from t1 to t4 is about 1:4.
During an operation to read data from the flash memory D0, the requested data may be moved from the flash memory device D0 to its internal buffer first. The data may then be transferred from the internal buffer of the flash memory device D0 to the flash controller 101. In the flash controller 101, the data may pass through the flash I/F controller 1013, the formatter 1012, and the ECC section 1011, and finally be sent to the host 102 through the buffer 103.
FIG. 1C illustrates the waveform of a read operation in the system shown in FIG. 1A. As shown, data may be moved from the flash memory device D0 to its internal buffer from time t0 to t3, and may be transferred from the internal buffer to the host from t3 to t4. Again, the host 102 is not involved in the transaction between the device D0 to its internal buffer, but the host 102 cannot do anything from t0 to t3, or t4 to t7. Consequently, considerable host time may be wasted.
Thus, it may be desirable to provide a solid state memory controller which may use the host time more efficiently.